Making chips perfect every time. The increasing need for mixed-signal design verification.
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Creating semiconductor chips "“ complex integrated circuits (IC) – is not for the faint of heart. Getting it right at the first attempt and on time to customer commitments can be a daunting task and "“ if missed "“ become a costly and time-consuming endeavor. Mixed-signal and full-chip IC design verification (DV) is critical to help prevent unnecessary silicon re-spins and ensure that every chip works perfectly "“ before it is delivered to the customer. As tools and methods have advanced, full-chip analog mixed-signal (AMS) simulations, analog auto-checking and automated data extraction techniques have all improved greatly over the last several years and play an increasingly important role in the design process. Scott will talk about recent advances in mixed-signal and automated design verification, cool new techniques for "breaking the part" in simulation, as well as the direction of TI's full-chip analog- and mixed-signal verification technology roadmaps.
Scott Morrison interned at TI in Dallas in 2000, finished his Masters in Electrical Engineering from the University of Florida in 2003, and then returned to TI starting as a digital design verification engineer verifying large PCI Express ASICs. Over the years, he moved toward mixed-signal and analog, leading verification teams for mixed-signal interfaces and high-speed SerDes. For the last three years, Scott has focused on verification of analog chips and specializes in mixed-signal design verification and deploying traditionally digital DV techniques such as constrained-random stimulus and auto-checking to analog and mixed-signal IC development. His areas of interest are rigorous automated verification, Verilog-AMS, behavioral modeling of analog circuits, and "beating the DUT [a1] to death." Scott was elected Senior Member of TI's Technical Staff (SMTS) in 2013 and is a driver of mixed-signal methodology improvements within TI to ensure every chip is perfect, every time.