A Review of the CHIPS for America Research and Development Programs

“Energy Efficient Circuits Beyond what have been believed as the Fundamental Limits: Power Converter, Analog Interface and Frequency Generation”

“Commercializing University Innovation – a non-linear journey”

The Analog Designers Toolbox (ADT): Towards A New Paradigm for Analog IC Design

The Programmable Matter Project: Realizing a matter made of autonomous robots

Analog Compute-in-Memory at Mythic

Run-time computation for enhanced integrated circuits and systems

The Simple Physics of Electronic, Thermal, and Electro-thermal Transport from the Nanoscale to the Macroscale

The Benefits of Mixed-Signal Computing for Neural Network Inference

Future Trends in Wireless Communications: 5G and Beyond

CMOS sensors: from cardiovascular signal to environmental monitoring

Nyquist-Rate Healthcare: Silicon Systems to Close the Sub-Sampling Gap in Health Monitoring

Tunable Cavities and Cold-Plasma Electronics for Reconfigurable RF Front-Ends

Ultra Low-Power Analog Front-End Design

Leveraging dense package technology in advanced technologies for large SoCs

Hardware and software progresses on designing programmable matter

IoT Sensing Device and Machine Learning

Continuous-time Pipeline ADC

Tunnel FET Modeling and Exploratory Circuit Design/Compiling Analog-to-Digital Converters

Tales of Commercializing Engineering Research and Related Irrational Endeavors

New Ingredients in the Pot – Rethink Analog IC Design

Microelectronics for Radiation Detectors

Ultra-Short-Reach Interconnects for Package-Level Integration

Wireless Trends & Emerging Applications in IoT & Wearables

Energy-Efficient Hardware for Embedded Vision and Deep Learning

Rethinking Analog-Digital Interface Circuit Architectures

How to transform a simple in LC-VCO into complete analog RF front-ends

Circuit Techniques for Next Generation Wireless Communication

Towards Interference-Free, Self-Organizing, Battery-Less Wireless Body Area Networks

Design techniques of SAR ADCs

Techniques to maximize dynamic range per unit consumption for wireless systems

The Coming Ethernet Revolution

Rethinking The Functional Boundaries of Integrated Radio-Frequency Systems Enables New Wireless Communication Paradigms

FinFETs: A Designers Perspective

TECH TRENDS ?? Observations on the Latest Buzzwords and the Changing Face of Innovation in Mixed Signal Processing

Making chips perfect every time. The increasing need for mixed-signal design verification.

High-Performance and Low-Voltage Circuits for Tera-Scale Multi-core Microprocessors and SoCs

Challenges of calibrated time-interleaved high-speed ADCs

Power Delivery in Heterogeneous Nanoscale Integrated Circuits

Serial Link and Channel Co-Design for Low Power Signaling on a Multi-Chip Module

Highly-Integrated CMOS Optical Transceivers

Medical Imaging: Technological Innovation that Can Improve Your Life

Neuromorphic Chip Design with a Scalable Architecture for Learning in Networks of Spiking Neurons

Successive Approximation and Time Interleaving for Sub-90nm CMOS ADCs

Holistic Circuits: or How I Learned to Stop Worrying and Love the End of Moores Law

Challenges in building resilient, energy-efficient processors and SoCs

Efficient Neural Computing using Cellular Array of Magneto-Metallic Neurons

Innovation at Texas Instruments How You Can Shape the Future

Inside Intel Logic Technology Development: Taking SRAM From 32nm Planar to 22nm Tri-gate Technology

Electronics for Interacting with a Physically-Complex World

Ubiquity of Wireless Sensor Nodes What are the Practical Challenges to Make it Happen?

Its About Time! (Making Best Use of Information in Time)

Wire line channels and equalization techniques for data transmission at speeds 10Gps and above

Beyond the Cloud Key Technologies and Challenges

Variability, Power, and Robustness in VLSI Design

Logic Technology Development's (LTD) Role in Advancing the Seminconductor Industry

Total Power-Optimal Pipelining and Parallel Processing under Process Variations in Nanometer Technology

The XScale Experience: Combining High Performance with Low Power on 0.18um through 90 nm Technologies

Design for Manufacturing effects in the nano-scale era

Efficient Retiming Algorithms for Wire Pipelining in System-on-Chip

Present and Future Challenges for Ultra-low Power Wireless SoC’s

Soft Errors: Interactions with Power Optimization

Design of Novel Performance-Optimized Silicon-based Integrated Circuits for Ultra-broadband Wireless/Wireline Communications

Challenges and Opportunities in High-Speed and Low-Power SRAM Design for Multi-Ghz Microprocessors

The Past, Present, and Future of PC Graphics and the Silicon Behind It

Low Power Circuits for Future Digital Systems

Energy Management for Battery-Powered Embedded Systems

An Architectural Perspective on Soft Errors in a High-Performance Microprocessor

Silicon Integration Choices in Sub-45nm Power Limited Microprocessors

Basic Concepts in Quantum Circuits

Sub-lithographic Semiconductor Computing Systems

VLSI Seminar

VLSI Seminar

A New Approach to Formal Design Verification

Moore's Law vs. Cost of Transistor Dilemma

Statistical Timing Analysis

VLSI Seminar

VLSI Seminar

Drowsy Caches: Simple Techniques for Reducing Leakage Power

Design Issues for High Performance ADCs

High Performance Microprocessor Design Using High-Radix Dynamic Logic

TBA

TBA

Low Power System On A Chip Design

Process and frequency scaling implications on high-frequency microprocessor CAD

Challenges and Opportunities for Mixed Signal Systems in Sub-100nm CMOS Technologies