A new hybrid chip that can change its own wiring

The speedy and efficient system-on-chip could unify wireless communication.

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As part of a national effort to advance electronics technology, Hun-Seok Kim, assistant professor of electrical and computer engineering, will lead a $5.2 million project to develop a new type of system-on-chip (SoC) that mixes together the adaptability of general purpose processors with the efficiency of specialized processors, allowing for demanding applications such as highly intelligent wireless communication systems used in radar and swarms of autonomous devices.

This hybrid SoC, the Domain-Focused Advanced Software-Reconfigurable Heterogeneous System on Chip (DASH-SoC), could allow for a unified, accurate and reliable wireless communication design that adapts to environments and needs through changes in software instead of hardware.

“Currently, wireless communications are supported by dedicated hardware modem designs tied to very specific international standards,” Kim said.

“However, there are tens of different standards, which prevents different applications from connecting when they use different wireless protocols. To connect these devices seamlessly, you need a unified solution, and the best way to approach this is to make the communication solution software-defined.”

The DASH processor could replace hardwired lines in places where communication is critical and requires speed and reliability, such as between autonomous cars and machines within factories. The technology could also offer a more robust solution for drones, localization services such as GPS and radar, and sensor networks in the Internet of Things.

The program, launched by the Defense Advanced Research Projects Agency (DARPA), is called Domain-Specific System on a Chip (DSSoC), and is a part of the Architectures research thrust area of its Electronics Resurgence Initiative (ERI). The DASH-SoC project, which is slated to receive $17 million in total funding throughout the life of the program, includes lead organization Arizona State University, University of Arizona, Carnegie Mellon University, Arm, General Dynamics, and EpiSys Science. David Blaauw, U-M professor of electrical and computer engineering, Trevor Mudge, U-M professor of computer science and engineering, and Ron Dreslinksi, U-M assistant professor of computer science and engineering, are also working with Kim.

We want to demystify this notion that there’s a fundamental tradeoff between flexibility and efficiency.

Hun-Seok Kim

Kim’s portion of the project is hardware integration, and will combine general purpose multi-core processors, like those found in our smartphones and tablets, and new domain-adaptive processors together with application-specific integrated circuit (ASIC) accelerators, which are hyper-optimized for a single task, such as deep neural network processing.

General purpose processors allow flexibility in their purpose, but at a lower speed and higher energy usage. On the other hand, the specialized construction of ASIC accelerators, which integrates a highly customized processing flow onto a single chip, allows them to quickly perform a single function at a lower power consumption. ASIC accelerators are designed with dedicated memory and processing elements in specific places for the best performance in their single tasks, often giving them 100 times the efficiency or greater compared to general purpose chips.

“We want to demystify this notion that there’s a fundamental tradeoff between flexibility and efficiency,” Kim said. “This new system will demonstrate that you can design an SoC that is not only flexible but also efficient.”

The DASH-SoC will combine innovative hardware and software to realize the benefits of both general purpose processors and accelerators. For hardware, the chip will utilize a new fast reconfigurable crossbar fabric, which will link the many memory and processing elements and allow for multiple pathways for data, much like a grid of city streets. The software, which includes an intelligent scheduler and resource manager, will determine the best pathways and direct data traffic based on a machine learning algorithm and the environmental and performance constraints. This allows the system to improve efficiency through reconfiguring its layout and resource allocation through software, instead of hardwiring an efficient design.

“The other approach to increase efficiency is to make the processor transform to handle frequently happening data patterns that are identified in a specific domain,” Kim said. “If you analyze many tasks in the communications systems, you’re going to identify some very common patterns in the data movement.”

This review of common data patterns within wireless communications, called an ontology interface, will be completed by Arizona State University.

“While we’re targeting a specific domain, the application space is huge,” Kim added. The same chip developed for wireless communications will also be adept with machine learning tasks, like image or audio classification.

To help developers utilize the new processor, further software tools, including debugging and compiling tools, libraries, and drivers will be created by another U-M team led by Dreslinksi and Mudge.

A related project in the Software-Defined Hardware program, which is within the Architectures research thrust of DARPA’s ERI, will work closely with the DASH-SoC project and share concepts and intellectual property. Arm, maker of Arm processors found in most smartphones, will also share key technology to help build this new type of processor.